1. Field of the Invention
The present invention relates to a circuit for generating two periodic signals having a controlled phase relationship and more particularly to circuitry which generates the two periodic signals with a phase relationship of from zero to 180 degrees, which phase is dependent on the amplitude of a d.c. control signal.
2. Description of the Prior Art
In many control systems an output parameter such as voltage, current or power is controlled by controlling the displacement angle between a primary waveform and a phase shifted version of the primary wave. The displacement angle may fluctuate anywhere from zero degrees to 180 degrees. Two well known prior art techniques for controlling this displacement angle are either the use of a phase-locked loop or the use of a delay timer system. The phase-locked loop system locks two oscillators into frequency synchronization and controls the phase angle between them by manipulating the phase detector parameters. The phase-locked loop system is, however, subject to problems. These problems arise as a result of instabilities in the control loop and difficulties in the operation of the capture and track modes of the phase locked-loop. When used as part of a larger control system these problems may make the larger system extremely difficult to stabilize.
The delay timer system has a main oscillator for generating the primary waveform. The secondary or phase shifted version of the primary waveform is generated by setting a delay. The delay is set as a predetermined time from the zero angle point. The principal problem with the delay timer system is that it is quite difficult to reduce the phase angle below a predetermined set point. This difficulty arises because of minimum output pulse restrictions imposed on most commercially available timing circuits.
The circuit of the present invention allows the phase angle between the main output and the phase shifted version thereof to vary between zero degrees and 180 degrees without any of the problems associated with the previously described phase-locked loop and delay timer systems.